Digital-to-analog converters are widely used for converting digital signals to corresponding analog signals for many electronic circuits. For example, a high resolution, high speed digital-to-analog converter (DAC) may find applications in cellular base stations, wireless communications, direct digital frequency synthesis, signal reconstruction, test equipment, high resolution imaging systems and arbitrary waveform generators, for example.
An integrated circuit DAC is described, for example, in U.S. Pat. No. 3,961,326 to Craven entitled "Solid State Digital to Analog Converter". The DAC includes binarily scaled constant current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a current summing bus or to ground. Each of the switch cells includes a first differential transistor pair driving a second differential pair of current switching transistors.
An article entitled "A 16-b D/A Converter with Increased Spurious Free Dynamic Range" by Mercer in the IEEE Journal of Solid-State Circuits, Vol. 29, No. 10, October 1994, pp. 1180-1185 discloses another DAC. The article identifies the two broad categories of errors or distortion in digital-to-analog conversion. Segmentation of the bits and laser trimming of thin film resistors are often used to minimize static errors. Dynamic or AC errors include nonlinear settling, ringing, non-symmetric slew, and glitch. Thermometer decoding of the most significant bits along with high-speed process technologies are often employed to minimize the dynamic errors. Segmentation of the four most significant bits into 15 currents of equal size is disclosed. An R/2R ladder is used with the 12 current sources for the least significant bits. Laser trimmable thin-film resistors are used in the DAC current sources to allow trimming to reduce linearity errors.
Unfortunately when a DAC switches from one code to the next there typically exists some asymmetry in the speed that the bit switch turns on and turns off. This results in the output of the DAC going in the wrong direction for a short time until all of the switches have fully switched. The resulting error or glitch in the output is code dependent and thus produces harmonic distortion or other nonharmonic spurs in the output spectrum. Glitch is often tested at the major carry of the DAC and there will be a spike in the output as the DAC switches. Glitch is typically considered as the net area under that spike.
There have been attempts to further reduce glitch in a DAC and thereby reduce harmonic distortion and other spurs in the output spectrum. For example, a DAC for video applications is disclosed in an article entitled "A Low Glitch 10-bit 75-MHZ CMOS Video D/A Converter" by Wu et al. in the IEEE Journal of Solid-State Circuits, Vol. 30, No. 1, January 1995. The DAC includes a segmented antisymmetric switching sequence and an asymmetrical switching buffer. The DAC includes a large number of non-weighted current sources for the seven most significant bits, and weighted current sources for the three least significant bits. The current sources may be non-uniform for various reasons, such as layout mismatch, thermal distribution, and process deviation. A segmented antisymmetric switching sequence is disclosed to suppress the superposition of graded error, symmetrical error, and especially random error. The asymmetrical switch control avoids simultaneously turning off the differential switching transistors completely, but allow simultaneous turn-on for a short period of time.
An article entitled "Matching Properties of MOS Transistors" by Pelgrom et al. appearing in the IEEE Journal of Solid-State circuits, Vol. 24, No. 5, October 1989, pp. 1433-1439 discloses that mismatch is the process that causes time-independent random variations in physical quantities of identical designed devices, and is a limiting factor in DACs, for example. Many known processes which cause mismatching include distribution of ion-implanted, diffused, or substrate ions; local mobility fluctuations; oxide granularity; oxide charges; etc. In particular, the article discloses that edge roughness seems not to be a major mismatch factor, leaving mobility and gate oxides as possible mismatch causes. The relative effect on the mismatch due to the distance is only significant for large-area devices with a considerable spacing. Correlation of the threshold-voltage variations with the current-factor variations shows that there is no significant mutual component for closely spaced transistor pairs; gate-oxide granularity is consequently not an important mismatch cause that affects both threshold voltage and current factor. It is reported that the threshold mismatch nearly halves with gate oxides thinner by a factor of two, whereas the current-factor mismatch remains constant. The variance of the threshold voltage, the current factor, and the substrate factor are inversely proportional to the transistor area. The mismatch in the threshold voltage dominates the transistor performance for normal gate-source potentials.
An article entitled "An 80-MHZ 8-bit CMOS D/A Converter" by Miki et al. in the IEEE Journal of Solid-State Circuits, vol. Sc-21, No. 6, December 1986, pp. 983-988, discloses a current cell matrix configuration to relax the mismatch problem of small-size transistors in a DAC. The linearity error caused by an undesirable current distribution of the current sources is described as having been reduced by symmetrical switching in a single dimension of the matrix as shown in FIG. 10 of the article. Unfortunately, as DACs become larger and operate at higher speeds, process variations and gradients may still impose relatively high non-linearities in a DAC even with symmetrical switching in one dimension of the current source array.